MOSFET fabricated on silicon on insulator (SOI) substrate provides an advantage for high speed and low power applications because of the low parasitic capacitance and the low body effect present in SOI structures. As CMOS IC technology enters the sub-50 nm range, the silicon channel and the buried oxide thicknesses must be less than 50 nm and 100 nm, respectively, in order to prevent the short channel effect (SCE), as described by R. Koh in Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 um SOI-MOSFET Jpn. J. Appl. Phys., Vol. 38, P. 2294 (1999); and R. Chau et al., A 50 nm Depleted-Substrate CMOS Transistor, IEDM, p. 621, 2001.
SiGe MOS transistors have been fabricated on tensile-strained silicon. The structure consists of a thick layer of graded Si1−xGex where x varies from zero at the bottom of the layer to about 0.3 at the top of the layer. The total layer thickness is on the order of 1 μm to 5 μm. The top of this graded SiGe is relaxed. A layer of 200 nm to one micron of relaxed Si1−xGex is grown on top of the graded SiGe layer, and a tensile-strained silicon epitaxial layer is deposited on the Si1−xGex layer. This structure is able to enhance the field effective electron mobility by ˜80% from that of a pure silicon device, Welser et al., Electron mobility enhancement in strained-Si N-type metal-oxide-semiconductor field-effect transistors, IEEE EDL-15, #3, p. 100, (1994); Rim et al., Transconductance enhancement in deep submicron strained-Si n-MOSFETs, IEDM Proc. p. 707 (1998). For pMOST, an effective hole mobility improvement of 30% over bulk silicon has been obtained, Rim et al., Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs, IEDM Proc. p. 517 (1995). However, the graded SiGe layers relax by generation and propagation of dislocations. This process typically results in an unacceptably high density of threading dislocations in the top SiGe and strained silicon of ˜1×107 cm−2, Paul, Silicon germanium heterostructures in electronics: the present and the future, Thin Solid Films, 321, p. 172 (1998), and references therein.
SiGe/SOI (silicon-on-insulator) transistors fabricated on a similar structure, but having silicon oxide buried in the relaxed graded SiGe layer, have also been fabricated, Mizuno et al., Advanced SOI-MOSFETs with strained—Si channel for high speed CMOS—electron/hole mobility enhancements, 2000 Symposium on VLSI, p. 210. The gain of hole mobility and electron mobility of this SiGe/SOI structure is higher than that of silicon control transistor by 45% and 60%, respectively. This structure is very complex, and the crystalline defect density is too high for large-scale integrated circuit application.
Another approach to form relaxed SiGe with a tensile strained silicon cap is to use SOI substrates. One method requires deposition of a SiGe layer on SOI, using a high temperature oxidation to form a relaxed SiGe film with high Ge content, Tezuka et al., A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs, Jpn. J. Appl. Phys. 40, p. 2866 (2001). Strained silicon may then be grown on the relaxed SiGe film. Another method uses a so-called “compliant oxide” to fabricate relaxed SiGe films on an insulating substrate, Yin, et al., Strain relaxation of SiGe islands on compliant oxides, J. Appl. Phys. 91, p. 9716 (2002).
Another approach to form a relaxed SiGe layer having a tensile strained silicon cap thereon is to use hydrogen ion implantation, Mantl et al., Strain relaxation of epitaxial SiGe layers on Si (100) improved by hydrogen implantation, Nuclear Instruments and Methods in Physics Research B 147, p. 29, (1999); Trinkaus et al., Strain relaxation mechanism for hydrogen-implanted Si1−xGex/Si (100) heterostructures, Appl. Phys. Lett., 76, p. 3552, (2000). A strained, dislocation-free SiGe layer is grown and then implanted with a high concentration of hydrogen ions so that the hydrogen is at, or just below, the SiGe/Si interface. The wafer is then annealed. During annealing, the hydrogen forms cavities at the SiGe/Si interface, and a dense network of misfit dislocations form. The result is a very efficient relaxation of the SiGe layer, resulting in a low density of threading dislocations. Once a relaxed SiGe layer is formed, a tensile-strained silicon cap may be grown Mantl et al., Trinkaus et al., supra, or a relaxed, second SiGe layer may be grown, followed by deposition of a tensile-strained silicon cap.
Devices grown on SOI substrates have shown good electrical properties with low power consumption. However, SOI substrates are very expensive. An alternative is to use a conventional bulk silicon substrate and produce a buried insulating layer only in certain local regions, such as in the channel region. This can save cost and also facilitates system-on-chip integration. One approach to this is called “Silicon-on-Nothing” (SON), Jurczak et al., SON (Silicon On Nothing)—A new device architecture for the ULSI era, 1999 Symposium on VLSI, p. 29 (1999); Jurczak et al., Silicon-on-Nothing (SON)—an innovative process for advanced CMOS, IEEE Trans. El. Dev. Vol. 47, p. 2179 (2000). In this method, a strained, epitaxial SiGe layer is grown on a bulk silicon substrate, and an unstrained silicon cap is deposited on the epi-silicon. The wafer is patterned and etched with an etchant that highly selectively removes SiGe, but does not etch silicon. This leaves the silicon cap suspended over a gap. This gap may be left empty (silicon-on-nothing) or filled with a dielectric (local SOI).